MOS devices with continuous contact etch stop layer
US7732878B2 · kind B2 · utility
6Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2006 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Feb 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.