Patent · US Active

Transistor arrangement, integrated circuit and method for operating field effect transistors

US7733156B2 · kind B2 · utility

54Cited by

5References

25Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Ralf Brederlow · Poing, DE
Jeongwook Koh · Seoul, KR
Roland Thewes · Puchheim, DE

Key dates

Filing date	Sep 1, 2004
Grant date	Jun 8, 2010
Priority date	—
Expiry date	Jan 23, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03F2203/7215
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.