Noise-reducing transistor arrangement

US7733157B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ralf Brederlow · Poing, DE
• Jeongwook Koh · Seoul, KR
• Christian Pacha · Birkenfeld, DE
• Roland Thewes · Puchheim, DE

Key dates

• Filing date: Dec 3, 2004
• Grant date: Jun 8, 2010
• Expiry date: Jun 9, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.