Pulse width control for read and write assist for SRAM circuits
US7733686B2 · kind B2 · utility
22Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.