Patent · US Active

Asymmetrical SRAM cell with 4 double-gate transistors

US7733688B2 · kind B2 · utility

3Cited by

4References

9Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Bastien Giraud · Grenoble, FR
Amara Amara · Sceaux, FR

Key dates

Filing date	May 29, 2008
Grant date	Jun 8, 2010
Priority date	—
Expiry date	Aug 23, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The random access memory cell of SRAM type comprises an access transistor provided with a gate electrode connected to a word line. The access transistor is connected between a bit line and a gate electrode of a first load transistor itself connected to a gate electrode of a driver transistor and to a first source/drain electrode of a second load transistor. The first load transistor and the driver transistor, in series, form an inverter at the supply voltage terminals. At least the transistors not comprised in the inverter comprise two electrically independent gate electrodes. The second gate electrode of the access transistor is connected to the first gate electrode of the second load transistor and the second gate electrode of the latter is connected to the supply voltage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.