Inventor · Grenoble, FR

Bastien Giraud

24Patents
5h-index
31Co-inventors
65Inventor score

Filing activity: May 29, 2008 → Dec 6, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8482070B1 Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same Electricity 19 Active
US8969967B2 Self-contained integrated circuit including adjacent cells of different types Electricity 9 Active
US9092590B2 Method for generating a topography of an FDSOI integrated circuit Physics 6 Active
US9479168B2 Method for controlling an integrated circuit Electricity 5 Active
US9093499B2 Integrated circuit using FDSOI technology, with well sharing and means for biasing oppositely doped ground planes present in a same well Electricity 5 Active
US9542996B2 Device with SRAM memory cells including means for polarizing wells of memory cell transistors Electricity 4 Active
US9000840B2 Integrated circuit comprising a clock tree cell Electricity 4 Active
US9508434B2 Programmable-resistance non-volatile memory Physics 4 Active
US7733688B2 Asymmetrical SRAM cell with 4 double-gate transistors Physics 3 Active
US9449688B2 Device and method for writing data to a resistive memory Physics 2 Active
US8320198B2 SRAM memory cell with double gate transistors provided means to improve the write margin Physics 2 Active
US8937505B2 Integrated circuit comprising a clock tree cell Electricity 1 Active
US9136366B2 Transistor with coupled gate and ground plane Electricity 1 Active
US10910040B2 Memory circuit Physics 1 Active
US10559355B2 Device and method for writing data to a resistive memory Physics 1 Active
US9911737B2 Integrated circuit comprising transistors with different threshold voltages Electricity 0 Active
US10741565B2 3D SRAM circuit with double gate transistors with improved layout Electricity 0 Active
US10297319B2 Memory device with unipolar resistive memory cells with programmable resistive element end control transistor and set/reset operations of thereof Physics 0 Active
US10811087B2 Memory circuit capable of implementing calculation operations Physics 0 Active
US12046284B2 Electroforming process using an inversion-invariant linear ECC, and associated device Physics 0 Active
US12362011B2 SRAM with reconfigurable setting Physics 0 Active
US12119059B2 Write method for differential resistive memories Physics 0 Active
US10803927B2 Partitioned memory circuit capable of implementing calculation operations Physics 0 Active
US11043248B2 Circuit for detection of predominant data in a memory cell Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.