Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit)

US7734968B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Richard J. Grupp · Colchester, US
• Kelly A. Ockunzzi · South Burlington, US
• Mark R. Taylor · South Burlington, US

Key dates

• Filing date: Jul 31, 2007
• Grant date: Jun 8, 2010
• Expiry date: Jul 30, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318519
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuits). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.