Common test logic for multiple operation modes
US7734972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2008 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Dec 6, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.