Early HSS Rx data sampling
US7735032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2007 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Sep 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A design structure includes a data communication circuit to facilitate communication between a deserializer, responsive to a serial data stream, which puts data onto a parallel bus, and a device that is in data communication therewith. The circuit a deserialization clock that asserts a clock read pulse each time data on the parallel bus is valid. A delay unit asserts a corresponding delayed clock pulse. The delayed clock pulse is delayed from the clock read pulse by a predetermined period. A clock tree repeats the delayed clock pulse and periodically asserts a plurality of end point repeated clock pulses, each of which has a substantially simultaneous leading edge. The predetermined amount of time is selected so as to cause each of the end point repeated clock signals to be asserted when data on the parallel bus is valid, thereby enabling the device to read data from the parallel bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.