Patent · US Active

Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit

US7735038B2 · kind B2 · utility

1Cited by

0References

7Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tobias Gemmeke · Santa Clara, US
Jens Leenstra · Nagold, DE
Jochen Preiss · Eppelheim, DE

Key dates

Filing date	Sep 6, 2007
Grant date	Jun 8, 2010
Priority date	—
Expiry date	Aug 13, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/0016
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.