Methods of estimating net delays in tile-based PLD architectures
US7735039B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2007 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Oct 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.