Production of two superposed elements within an integrated electronic circuit
US7736840B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 26, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Mar 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first circuit element, which is reflective, is formed. A first layer, which is attenuating, is formed. above the first circuit element. A second layer, which is transparent, is formed above the first layer to fill an aperture in the first layer. An overlying lithography resist layer is then exposed to a radiation flux level below a development threshold but high enough that a sum of the radiation flux level and a reflected secondary radiation flux level exceeds the development threshold. The lithography resist layer is developed so as to obtain a mask having an opening through which the first and second layers are removed to form a second aperture which is filled to form a second circuit element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.