Method and structure for optimizing yield of 3-D chip manufacture

US7737003B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Edward M. DeMulder · South Burlington, US
• Sarah H. Knickerbocker · Hopewell Junction, US
• Michael J. Shapiro · Austin, US
• Albert M. Young · Fishkill, US

Key dates

• Filing date: Oct 11, 2005
• Grant date: Jun 15, 2010
• Expiry date: Nov 27, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/13

Abstract

The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.