Semiconductor component having test pads and method and apparatus for testing same
US7737439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Apr 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0268
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.