Patent · US Active

Device control register for a processor block

US7737725B1 · kind B1 · utility

30Cited by

3References

15Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Ahmad R. Ansari · San Jose, US
Kam-Wing Li · San Jose, US

Key dates

Filing date	Apr 4, 2008
Grant date	Jun 15, 2010
Priority date	—
Expiry date	Jul 18, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/7867
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.