Method of and circuit for reducing distortion in a power amplifier
US7737779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Aug 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/3247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a circuit for reducing distortion in a power amplifier is disclosed. The integrated circuit comprises a predistortion circuit coupled to receive a signal to be amplified; sample capture buffers coupled to an output of the predistortion circuit and an input/output port of the integrated circuit; and an estimator circuit coupled to the sample capture buffers, wherein the estimator circuit generates parameters for the predistortion circuit based upon the output of the predistortion circuit and an output of the power amplifier received at the input/output port of the integrated circuit. A method of reducing distortion in a power amplifier is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.