Method to improve the write speed for memory products
US7738306B2 · kind B2 · utility
3Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | Dec 7, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.