Patent · US Active

Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto

US7738588B2 · kind B2 · utility

2Cited by

5References

20Claims

0Family size

Assignees

Infineon Technologies AG · DE
Robert Bosch GmbH · DE

Inventors

Jens Barrenscheen · Munich, DE
Peter Rohm · Brackenheim, DE
Axel Aue · Strohberg, DE
Jens Graf · Gochsheim, DE
Herman Roozenbeek · Schwieberdingen, DE

Key dates

Filing date	Dec 2, 2003
Grant date	Jun 15, 2010
Priority date	—
Expiry date	Jan 3, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG05B2219/24065
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The first semiconductor chip transmits appropriate pilot data in order to prescribe to the second semiconductor chip what transmission rate is to be used by the second semiconductor chip to transmit the diagnostic data to the first semiconductor chip.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.