Inspection plan optimization based on layout attributes and process variance
US7739065B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jun 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods for determining customized defect detection inspection plans are provided. One method includes fabricating a test chip and generating test chip data from the fabricated test chip. Then, defining systematic signatures from the generated test chip data and identifying a yield relevant systematic signature from the defined systematic signatures. The method includes identifying a layout pattern associated with the yield relevant systematic signature and locating the identified layout pattern on a process module layer of a product chip. Further, the method includes defining a customized defect detection inspection or metrology methodology for detecting systematic defects on the process module layer based on the identified layout pattern associated with the yield relevant systematic signature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.