Fast hardware co-simulation reset using partial bitstreams
US7739092B1 · kind B1 · utility
29Cited by
12References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Apr 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.