Communicating between a native fully buffered dual in-line memory module protocol and a double data rate synchronous dynamic random access memory protocol
US7739441B1 · kind B1 · utility
20Cited by
13References
18Claims
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Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Sep 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A translator of an apparatus in an example communicatively interconnects a serial protocol bus that follows a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) and three or more parallel protocol memory module channels that comprise a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.