System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation
US7739570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jul 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.