Patent · US Active

Method and mechanism for implementing electronic designs having power information specifications background

US7739629B2 · kind B2 · utility

28Cited by

12References

29Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Qi Wang · Malden, US
Ankur Gupta · Bengaluru, IN
Pinhong Chen · Saratoga, US
Christina Chu · San Jose, US
Manish Pandey · San Jose, US
Huan-Chih Tsai · Saratoga, US
Sandeep Bhatia · Savanuru, IN
Yonghao Chen · Groton, US
Steven Sharp · North Berwick, GB
Vivek Chickermane · Ithaca, US
Patrick Gallagher · Apalachin, US

Key dates

Filing date	Oct 30, 2006
Grant date	Jun 15, 2010
Priority date	—
Expiry date	Jul 6, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.