Optimizing a circuit design
US7739630B1 · kind B1 · utility
8Cited by
1References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Apr 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.