Method of manufacturing semiconductor device

US7741185B2 · kind B2 · utility

Assignee

• FUJITSU SEMICONDUCTOR LIMITED · JP

Inventor

• Ryo Tanabe · Kyoto, JP

Key dates

• Filing date: Jul 2, 2008
• Grant date: Jun 22, 2010
• Expiry date: Jul 8, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227

Abstract

Each of channel regions 2a and 3b is covered by a gate electrode 6 via a gate insulation film 5 and side wall spacers 9 from its top face to both side faces along an x-direction. In other words, there is no insulation material of an STI element isolation structure 4 on both side faces along the x-direction of each of the channel regions 2b and 3b (in a non-contact state), thereby preventing stress in a z-direction from being applied by the STI element isolation structure 4 to each of the channel region 2b and 3b.