Post last wiring level inductor using patterned plate process
US7741698B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2008 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Jul 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.