Differential on-line termination
US7741867B2 · kind B2 · utility
6Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2008 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Oct 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.