Dynamic random access memory with low-power refresh
US7742355B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2007 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Aug 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to reduce refresh power in a DRAM. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Testing the DRAM uses a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.