Optimizing integrated circuit design through use of sequential timing information
US7743354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2007 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Jul 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.