Gate self aligned low noise JFET

US7745274B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Xiaoju Wu · Irving, US
• Fan-Chi Hou · McKinney, US
• Pinghai Hao · Plano, US

Key dates

• Filing date: Mar 8, 2007
• Grant date: Jun 29, 2010
• Expiry date: Dec 16, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/87

Abstract

The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.