Methods of manufacturing trench isolated drain extended MOS (demos) transistors and integrated circuits therefrom

US7745294B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Sameer Pendharkar · Allen, US
• Binghua Hu · Plano, US

Key dates

• Filing date: Nov 10, 2008
• Grant date: Jun 29, 2010
• Expiry date: Nov 10, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0191

Abstract

A method of fabricating an integrated circuit (IC) including at least one drain extended MOS (DEMOS) transistor and ICs therefrom includes providing a substrate having a semiconductor surface, the semiconductor surface including at least a first surface region that provides a first dopant type. A patterned masking layer is formed on the first surface region, wherein at least one aperture in the masking layer is defined. The first surface region is etched to form at least one trench region corresponding to a position of the aperture. A dopant of a first dopant type is implanted to raise a concentration of the first dopant type in a first dopant type drift region located below the trench region. After the implanting, the trench region is filled with a dielectric fill material. A body region is then formed having a second dopant type in a portion of the first surface region. A gate dielectric is then formed over a surface of the body region and the first surface region. A patterned gate electrode layer is formed over the gate dielectric, a source region in the body region and a drain region in the first surface region on a side of the trench region opposite to the source are formed, a…