Nitride-based semiconductor device with reduced leakage current
US7745850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Aug 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high electron mobility transistor is disclosed which has a triple-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. Whilst the aluminum nitride layers are of n-like conductivity, the gallium nitride layers are doped into p-type conductivity, with the consequent creation of pn junctions between the two kinds of buffer layers. Another pn junction is formed between one p-type gallium nitride layer and the adjoining n-like electron transit layer included in the main semiconductor region. The pn junctions serve for reduction of current leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.