Multiple-level memory with analog read
US7746692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2008 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Aug 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge. An analog multiplexer is connected to the sense amplifiers. The analog multiplexer is operative to receive the respective analog signals from the sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the sense amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.