System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation

US7747908B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Shubhodeep Roy Choudhury · Savanuru, IN
• Manoj Dusanapudi · Bengaluru, IN
• Sunil Suresh Hatti · Gokul, IN
• Shakti Kapoor · Austin, US
• Chakrapani Rayadurgam · Savanuru, IN
• Batchu Naga Venkata Satyanarayana · Savanuru, IN

Key dates

• Filing date: Jul 18, 2007
• Grant date: Jun 29, 2010
• Expiry date: Dec 18, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/263
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation is presented. A test pattern generator/tester re-uses test patterns in different configurations that alter cache states and translation lookaside buffer (TLB) states, which produces different timing scenarios on a broadband bus. The test pattern generator/tester creates multiple test patterns for a multi-processor system and executes the test patterns repeatedly in different configurations without rebuilding the test patterns. This enables a system to dedicate more time executing the test patterns instead of building the test patterns. By repeatedly executing the same test patterns in a different configuration, the invention described herein produces different start cache states, different TLB states, along with other processor units, each time the test patterns execute that, in turn, changes the bus timing.