Correcting intermittent errors in data storage structures
US7747913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2007 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Dec 22, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of apparatuses and methods for correcting intermittent errors in data storage structures are disclosed. In one embodiment, an apparatus includes a data storage location, error detection logic, inverting logic, control logic, operating logic, and evaluation logic. The error detection logic is to detect an error in a data value read from the data storage location. The inverting logic is to invert the erroneous data value to produce an inverted erroneous data value. The control logic is to cause the inverted erroneous data value to be stored in the data storage location and subsequently read from the data storage location to produce an operand value. The operating logic is to perform a logical operation using the erroneous data value and the operand value. The evaluation logic is to evaluate the result to determine if the error is a soft error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.