Method and apparatus for detecting communication errors on a bus
US7747933B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2005 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Nov 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.