Integrated circuit modeling, design, and fabrication based on degradation mechanisms

US7750400B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Ajit Shanware · Cupertino, US
• Srikanth Krishnan · Richardson, US

Key dates

• Filing date: Aug 15, 2008
• Grant date: Jul 6, 2010
• Expiry date: Mar 17, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).