Self-aligned complementary LDMOS
US7750401B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 9, 2009 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Jun 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.