Memory repair system and method
US7751264B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Aug 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/789
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) comprises a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module detects defective memory locations in the memory module, locates redundant memory elements in the memory module, and stores information that associates memory addresses of the defective memory locations with the redundant memory elements in the memory repair database. Storing said information includes electrically altering at least one of a plurality of electrical fuses. A redundant memory decoder module receives the information and physically remaps the memory addresses to the redundant memory locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.