Extended synchronized clock
US7751274B2 · kind B2 · utility
1Cited by
16References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2006 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Oct 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments are directed to circuits comprising first and second PLLs. The first PLL generates a first clock signal based on a reference clock signal. The second PLL generates a second clock signal based on the reference clock signal and is synchronized with the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.