Version based non-volatile memory translation layer
US7752381B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 2005 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | May 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data updating and helps reduce program disturb of the memory cells of the non-volatile memory device. The various embodiments utilize a version number associated with each erase block, data block, sector, and/or cluster. This allows for determination of currently valid data block, sector and/or cluster associated with the logical ID of the data grouping by locating the most recent version associated with the logical ID. With this approach, old data need not be invalidated by programming a valid/invalid flag, avoiding the risk of program disturb in the surrounding data rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.