Fast transition from low-speed mode to high-speed mode in high-speed interfaces
US7752476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2007 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Feb 17, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.