Reduced-complexity decoding of parity check codes
US7752523B1 · kind B1 · utility
156Cited by
2References
42Claims
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Key dates
| Filing date | Oct 16, 2006 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | May 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosed technology provides a less resource intensive way to decode a parity check code using a modified min-sum algorithm. For a particular parity check constraint that includes n variable nodes, an LDPC decoder can compute soft information for one of the variable nodes based on combinations of soft information from other variable nodes, wherein each combination includes soft information from at most a number d of other variable nodes. In one embodiment, soft information from one of the other variable nodes is used in a combination only if it corresponds to a non-most-likely value for the other variable node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.