Design structure and system for identification of defects on circuits or other arrayed products
US7752581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2007 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Aug 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is select to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.