Patent · US Active

FPGA having a direct routing structure

US7755387B2 · kind B2 · utility

3Cited by

5References

19Claims

0Family size

Assignee

Sicronic Remote KG, LLC · US

Inventors

Deboleena Minz · New Delhi, IN
Kailash Digari · Noida, IN

Key dates

Filing date	Nov 1, 2005
Grant date	Jul 13, 2010
Priority date	—
Expiry date	Feb 19, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17732
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An improved FPGA having a direct interconnect structure to provide selective data routing without stressing the general-purpose routing resources and to enable high rate of data exchange within the FPGA. At least two IP cores are connected to each other through the direct interconnect structure to enable simultaneous data interaction among the ports of the IP cores and to provide configurable bus width routing between the IP cores, and a plurality of logic blocks connected to the IP cores through the direct interconnect structure to enable simultaneous data routing among the IP cores and the plurality of logic blocks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.