Integrated circuit memory device having dynamic memory bank count and page size
US7755968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2007 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Aug 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.