Patent · US Active

Synchronizing recency information in an inclusive cache hierarchy

US7757045B2 · kind B2 · utility

12Cited by

4References

23Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Christopher Shannon · Selkirk, CA
Ronak Singhal · Portland, US
Per Hammarlund · Hillsboro, US
Hermann W. Gartler · Portland, US
Glenn J. Hinton · Portland, US

Key dates

Filing date	Mar 13, 2006
Grant date	Jul 13, 2010
Priority date	—
Expiry date	Oct 30, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/123
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, the present invention includes a method for receiving a cache access request for data present in a lower-level cache line of a lower-level cache, and sending recency information regarding the lower-level cache line to a higher-level cache. The higher-level cache may be inclusive with the lower-level cache and may update age data associated with the cache line, thus reducing the likelihood of eviction of the cache line. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.