Patent · US Active

Methods and systems for implementing dummy fill for integrated circuits

US7757195B2 · kind B2 · utility

10Cited by

75References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Taber H. Smith · San Jose, US
Vikas Mehrotra · London, GB
David White · San Jose, US

Key dates

Filing date	Dec 18, 2006
Grant date	Jul 13, 2010
Priority date	—
Expiry date	Dec 6, 2027

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P90/02
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.