Scan chain systems and methods for programmable logic devices
US7757198B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Dec 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods provide techniques to support design specific testing for programmable logic devices in accordance with one or more embodiments. For example in one embodiment, a method of generating configuration data for a programmable logic device includes mapping a design for the programmable logic device, wherein the mapped design incorporates scan test logic; placing and routing the mapped design; and generating configuration data based on the mapped design, wherein the incorporated scan test logic is disabled and not selectable within the programmable logic device configured with the configuration data. The method may further include generating a second configuration data based on the mapped design, wherein the incorporated scan test logic is enabled and selectable within the programmable logic device configured with the second configuration data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.