Methods for charge dissipation in integrated circuits

US7759173B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kenneth L. DeVries · Salt Lake City, US
• Nancy Anne Greco · Lagrangeville, US
• Joan Preston · Wimberley, US
• Stephen L. Runyon · Pflugerville, US

Key dates

• Filing date: Apr 15, 2008
• Grant date: Jul 20, 2010
• Expiry date: Jan 9, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.